DRAM read

We have not talked about some problems, such as the CAS-2 and CAS-3 the difference between what we are concerned. Now we already have a basic understanding of the basics for the DRAM, the following article is to introduce some modern memory technology. DRAM reading process is actually in the previous article discussed the DRAM read and write, but in the previous presentation in memory, a better understanding of friends will find only the memory generally read a brief description of many The important details are not discussed in detail. Therefore, we in the contents of this section of the article for a detailed discussion of this process. Here is the asynchronous memory read process steps do not need to because the asynchronous DRAM running the same processor, same frequency, the operation of the control timing signal, addressing basically independent control by the memory chip itself control, so in the discussion of them relatively simple, we only need to consider the case of the DRAM itself (this series of articles is in line with the principle of gradual and orderly progress, so that we better understand the working principle of the memory):
1) The row address through the address bus transfer to the address pins.
2) / RAS pin is activated, the column address will be placed in the row address strobe circuit (Row Address the Latch: In the front part of the article it translated into the column address latch circuit).
3) The row address decoder (Row Address Decoder) to select the correct line and then sent to the sense amplifiers (sense amps).
4) / WE pin is not activated, so the DRAM knows that they are not to write.
5) the column address to the address pins via the address bus transfer.
6) / CAS pin is activated, the column address can be sent to the column address strobe (Column Address the Latch).
7) / CAS pin as an output start signal (Output Enable)  / CAS signals on the sensing amplifier, has been found because of the much needed data, Dout pin valid, the data from memory be transmitted to the system.
8) / RAS and / CAS pin stop activated, wait for the next read command.
Memory read, we need to consider two main types of delay. The first category is the delay between consecutive DRAM read operation. Memory can not be in progress finished a read operation as soon as the first two read operations, because the DRAM read operation, including charging and discharging of the capacitor also includes the time of the signal sent in two read operations the middle, leave at least enough time to let the memory of these aspects of the operation. Between two consecutive read operation, the first type of delay / RAS and / CAS precharge delay time.  / RAS is activated and deactivation, you must give it enough time to prepare for the next activation.
Of course, in between the two read operations precharge time is not to limit the DRAM speed the only factor. The second delay type is called the internal (inside-the-read) read latency. This delay is the delay between the same two read operations are very similar, but not activated by the stop / RAS and / CAS, but due to the activation / RAS and / CAS. For example, the row access time (tRAC) - it is activated RAS and the data will ultimately appear in the time between the data bus. The same column access time (tCAC) is activated / CAS pin and the data will ultimately appear in the time between the data bus.
Now let's spend a little time to combine the read process described above to study this diagram above:
1) first took a fancy to the first row of the diagram, this period RAS is not activated, we see the data in the third line of the Address the BUS line on the address bus during this period in the pre-charge during the row address to the address pins via the address bus transfer this period the CAS in a precharge state;
2) still took a fancy to the first line in the Figure, the / RAS pin is activated (RAS Active, the gray part), the column address will be placed in the row address strobe circuit (the third line of Address
Bus below) during CAS is still in the pre-charge state; / RAS is activated at the same time, tRAC (row access time) - as shown above the last line of the Data Bus, as shown.
3) After / RAS is activated, the row address decoder (Row Address Decoder) to select the correct line and then sent to the sense amplifiers (sense amps).
4) During this period, the / WE pin has been in an activated state, so the DRAM knows that they are not to write. This state will continue to start write operation until the end.
5) the column address to the address pins via the address bus transfer.
6) / CAS pin is activated (as shown above the third line), the column address can be sent to the column address strobe control (Column Address the Latch). This the time tCAC (column address access time) to start timing.
7) is active during the end of the / CAS / RAS activation is stopped - also about the data found in the vicinity of this time sent to the data bus for data transfer (Figure data Bus), the data bus for data transfer process, the address bus is idle, it does not accept the new data - sent in the data record at the same time tRAC and tCAC end.
8) during the data transmission on the data bus, the / CAS pin is stopped activation - is a high level, which began to enter into pre-charge period.
RAS and CAS will also be in the pre-charge period, until the next / RAS activation cycle to the next read operation. I believe that such instructions should be aware of the DRAM read. On this basis, we can begin to recognize the SIMM or DIMM latency (latency) problem. First of all, we continue to clarify a few concepts. DRAM latency types are divided into two types: access time (access time) and cycle time (cycle time). Access time (access time) with the front we are talking about the second type of delay is related with the read cycle delay time; cycle time (cycle time) in front of us talking about the first type delay , which is subject to the impact of the delay time between the two read cycles. Of course, the incubation period is very short, measured in nanoseconds.
As of asynchronous DRAM chips, the access time is to reach the row address pins from the row address from the time data is transmitted to the data pins of the time. In this way, the access time is 60 ns DIMM means that when we issued the command to read data, address data is sent to the address pins to wait 60 nm in order to achieve data output pin. Cycle time, literally from two sequential read time interval between the operations. How to reduce the DRAM cycle time and access time is the second half of this article will be discussed in detail.
We usually comes to DRAM memory is many nanoseconds here refers to the general (we will explain) Why take the nominal access time. We all know that the shorter the access time, means that the memory operating frequency will be higher. Of course, the higher the memory operating frequency means that you can adapt to the higher FSB of the processor. If the processor clock cycle is short and the long incubation period of the DRAM, the processor in a lot of time to wait for the DRAM transfer data. Therefore, when the DRAM must, such as incubation period is 70 ns, then one must wait for data 1GHz a PIII will be longer than a 400MHz PII, processor. Course, such a phenomenon is that each user would like to see, when the memory used by the slower or the faster your processor is relatively Yourprocessor will be more performance have been waiting such a wasted.